1. Field of the Invention
The present invention relates to a phase generator for introducing phase shift in a signal.
2. Description of the Related Art
Fundamentally in electronic design, synchronous operation is essential for ensuring that logic operations are being performed correctly. In a system, an integrated circuit may generate its own internal clock based on the master clock signal. Differences in clock signal arrival across the chip, which is called clock-skew, must be avoided. In order to ensure proper operation, it is often important to reduce clock skew for the internal clock of the integrated circuit. Conventionally, more hardware is put into a single chip due to which the complexity on the chip is increasing. It is a fundamental design principle that timing must satisfy register setup hold time requirement. So the clock-skew can potentially cause timing violations or even functional failure of a chip.
Clock skew being a major problem PLL (phase locked loop) is becoming an integral part of the System on Chips (SOCs). In field programmable gate arrays (FPGA) or SOC chips, PLLs are generally employed to provide clock synchronization or to eliminate the clock skew. The other features which PLL supports are the frequency multiplication, programmable duty cycle or programmable phase shift. Programmable phase shift circuit provides an output clock, which has a phase difference with respect to the input clock.
U.S. Pat. No. 6,667,641 provides a programmable phase shift feature for a phase locked loop circuit. The phase shift may be adjusted with equal steps. Each step may be a fixed percentage of the clock period.
FIG. 1 shows a conventional phase generator for a phase locked loop. The outputs of the voltage controlled oscillator (VCO) stage 1620 are mixed together with a multiplexer 1625. The multiplexer is configurable, which is controlled by configuration bits from a configuration register 1633. The output of the multiplexer 1625 is fed back to the phase detector 1610 through a frequency divider 1630. The output clock of the PLL is connected to stage A of the VCO. If the feedback is not mixed from stage A, the output clock will have a phase shift compared with the input clock. The amount of the phase shift is determined by number of stages between A and feedback.
Referring to the FIG. 2, it describes an 8-phase Voltage controlled oscillator. It consists of four differential delay cells 31. ‘Ctrl’ is the control voltage to each differential delay cell. The outputs of each stage are applied to the inputs of the next stage, but the output ‘out’ of the forth delay cell is applied to ‘in2’ of the first input and output ‘outbar’ of the last delay cell is applied to the input ‘in1’ of the first delay cell. The eight outputs OT1, OT2, . . . , OT8 are the eight phases each 45-degree apart.
By programming MUX1, a user can adjust the phase difference between the output clock and input clock. This phase difference will be a fixed percentage of the output clock period. It is therefore required that additional phase shift is induced in the output of the PLL besides said fixed percentage of output clock period.